1. Field of the Invention
The present invention relates to a semiconductor device and a method of measuring a sheet resistance of a lower layer conductive pattern thereof and, more particularly, to a semiconductor device containing an element configured by sandwiching an insulating layer between a lower layer conductive pattern and an upper layer conductive pattern, the outline of which is smaller than that of the lower layer conductive pattern, and to a method of measuring a sheet resistance of the lower layer conductive pattern.
2. Description of the Related Art
As the semiconductor device process becomes finer and the semiconductor device performance becomes higher, it has become increasingly important to extract the exact parasitic effect of an element fabricated on a semiconductor substrate. In an analog circuit in particular, since the parasitic effect has a significant influence on electric power and electrical operation, it has become important to measure the exact parasitic effect and perform high-precision circuit simulation using the results of measurement.
For example, Japanese Patent Laid-Open No. 2001-313323 discloses an evaluation pattern whereby it is possible to measure the sheet resistance of a MOSFET source-drain diffusion layer, particularly the sheet resistance in the gate length direction thereof and the resistance of a portion overlapping with a gate electrode.
Incidentally, some elements have two (small and large) values of parasitic resistance on the lower layer conductive pattern (lower electrode) of a substrate due to constraints on a production process for fabricating transistors and the like on the same substrate. Consequently, there is a problem that it is difficult to estimate the sheet resistance of a high-resistance portion since this portion is affected by the low-resistance portion of the lower layer conductive pattern (lower electrode).
Now, a detailed explanation will hereinafter be made in this regard with an example of a polysilicon-insulator-polysilicon (PIP) capacitive element wherein the above-described problem surfaces notably.
<Structure of PIP Capacitive Element>
FIG. 6a is a plan view of a PIP capacitive element and FIG. 6b is a cross-sectional view showing the plane A-B of the PIP capacitive element. The PIP capacitive element is formed on a silicon oxide film formed on a silicon substrate. An effective capacitive portion is formed using an SiO2 dielectric film 15 (film thickness of approximately 10 to 40 nm) sandwiched between an upper electrode 14 and a lower electrode 13 (film thickness of approximately 150 to 300 nm) formed of polysilicon. At the time of circuit design, the surface area of the effective capacitive portion is determined so as to meet a desired value of capacitance. The upper electrode 14 and the lower electrode 13 are electrically connected to upper wire lines 19 through contacts 16.
<Production Process of PIP Capacitive Element>
FIG. 7 is a production process flowchart of a PIP capacitive element. An explanation will hereinafter be made of the production flow of the aforementioned PIP capacitive element with reference to FIGS. 6 and 7.
First, an oxide film 12 is provided on the entire upper surface of a silicon substrate 11 and the lower electrode 13 of the PIP capacitive element is formed on the entire upper surface of the oxide film 12 (Step S001).
Next, a dielectric film (oxide film) 15 is formed on the entire upper surface of the lower electrode 13 (Step S002).
Then, the upper electrode 14 is formed on the entire upper surface of the dielectric film (oxide film) 15 (Step S003).
Next, photoresist is formed into a predetermined shape on the upper electrode 14 and the upper electrode 14 is etched into a predetermined shape (Step S004).
Following the etching of the upper electrode 14, the dielectric film (oxide film) 15 is also etched into a predetermined shape (Step 005).
Next, after removing the photoresist, another photoresist is formed again into a predetermined shape so as to cover the remaining upper electrode 14 and part of the exposed lower electrode 13, in order to etch the lower electrode 13 into a predetermined shape (Step 006).
Then, the photoresist is removed and a treatment is made so as to silicide the surfaces of the exposed upper electrode 14 and the lower electrode 13 (portions in FIG. 6 indicated by reference numerals 18) and reduce the resistances thereof (Step 007). At this point, the resistance of a portion, among the portions of the surface of the lower electrode 13, covered with the dielectric film (oxide film) 15 and the upper electrode 14 is not reduced.
Finally, after the entire surface of the PIP capacitive element is covered with an insulating film and the film-covered surface is flattened, contacts 16 reaching the surfaces of the lower electrode 13 and the upper electrode 14 are respectively formed from the surface of the insulating film and upper wire lines 19 to be connected to the contacts 16 are provided, thus completing the PIP capacitive element shown in FIG. 6.
In the silicidation process of Step S007 described above, there are formed two types of regions having different sheet resistances in the lower electrode of the PIP capacitive element, i.e., a region which is not overlapped with the upper electrode 14 and the resistance of which is reduced and a region which is overlapped with the upper electrode 14 and the resistance of which is not reduced, since the resistance of a portion, among the portions of the lower electrode 13, overlapping with the upper electrode 14 is not reduced. Since these sheet resistances differ by approximately two orders of magnitude from each other and significantly contribute to the high frequency characteristics of the PIP capacitive element, it is necessary to precisely measure the values of both resistances and provide the results of measurement for simulation. However, since the high-resistance portion is short-circuited with the low-resistance portion as described above and, therefore, the low resistance is included in a measured value when an attempt is made to measure the parasitic component of the higher of these two resistances, it is difficult to precisely measure the value of the high-resistance portion.
Note that the above-described silicidation process is necessary in order to reduce the parasitic and contact resistances of the gate electrodes, sources, drains and contacts of transistors mixedly formed on the same wafer. In addition, for reasons of the production process of the PIP capacitive element, there is a constraint that the silicidation process must unavoidably be performed after film-forming the upper electrode.
Under the premise noted above, the inventors of the present application have considered measurement patterns for measuring the values of two types of parasitic resistances present in the above-described lower electrode. Now, an explanation will be made of problems with these measurement patterns.
<Measurement Pattern 1 Considered>
FIG. 8a is a plan view of Measurement Pattern 1 considered and FIG. 8b is a cross-sectional view of the plane A-B of the measurement pattern. As shown in the cross-sectional view of FIG. 8b, Measurement Pattern 1 has a layout wherein the lower electrode 13 is transversally covered by the upper electrode 14 so that any low-resistance portion (silicided portion) is not formed between the contacts 16 at the time of silicidation treatment. In other words, the short-circuiting current path of the silicided portion is shut off at the upper electrode 14 so that any short-circuit component due to the low-resistance portion (silicided portion) does not develop when measuring the high-resistance portion of the lower electrode 13, thereby making it possible to precisely measure the resistance value of the high-resistance portion. Note that in Measurement Pattern 1, there are disposed as many contacts 16 as possible for electrical connection between upper wire lines 20 for measurement and the lower electrode 13, in order to reduce the parasitic resistance component resulting from measurement. Each of upper wire lines 20 is connected to a corresponding pad(not shown in the figure) for measuring resistance of the high-resistance portion.
<Problems With Measurement Pattern 1 Considered>
To create Measurement Pattern 1, the lower electrode 13 must be formed smaller than the upper electrode 14 at least in the crosswise (width) direction of FIG. 8. However, in the production flow of FIG. 7 described above, the exposed lower electrode 13 can only be etched by first film-forming the lower electrode 13, the dielectric film (oxide film) 15 and the upper electrode 14 on the entire surface of the PIP capacitive element, and then etching from the uppermost surface to the upper electrode 14 and the dielectric film (oxide film) 15 in this order. Consequently, in the production flow shown in FIG. 7, it is not possible to form the lower electrode 13 smaller than the upper electrode 14.
In order to form the lower electrode 13 smaller than the upper electrode 14, the order of steps shown in the production flow of FIG. 7 must be changed. For example, the order of steps may be changed so that the film-formation of the lower electrode (Step S001) and pattern formation (etching) (Step S006) are followed by the formation of the oxide film (Step S002), the film-formation of the upper electrode (Step S003) and the etching of the upper electrode (Step S004).
However, such a change in the order of steps as described above is hardly acceptable since it also means a change in the steps of the production process flow of the PIP capacitive element and has a significant influence on the production steps of transistors contained in the same wafer. In addition, such a change requires process development for the purpose of creating the measurement pattern and, therefore, this measurement pattern is inadvisable also from the viewpoint of development turnaround time and costs.
Another point to note is that since the production process is made to differ from the normal production steps of the PIP capacitive element, Measurement Pattern 1 has the problem that it is not possible either to precisely monitor the sheet resistance of the lower electrode in the production steps of the PIP capacitive element.
<Measurement Pattern 2 Considered>
FIG. 9a is a plan view of Measurement Pattern 2 considered and FIG. 9b is a cross-sectional view of the plane A-B of the measurement pattern. Measurement Pattern 2 differs from Measurement 1 in that the width (A-B direction in FIG. 9) of the upper electrode 14 has been made to agree with that of the lower electrode 13 so that there is no need to change the order of steps in the existing production flow. This Measurement Pattern 2 is also adapted so that any low-resistance portion (silicided portion) is not formed between contacts 16. Thus it is possible to precisely measure the resistance value of a high-resistance portion.
<Problems With Measurement Pattern 2 Considered>
However, in order to create Measurement Pattern 2, patterning must be performed online so that both ends of the upper electrode 14 agree with those of the lower electrode 13. For process reasons, it is extremely difficult technically to form a pattern without allowing the lower electrode 13 to shift from the upper electrode 14.
Considering that it is difficult to perform patterning completely online and that there may occur a mismatch in mask alignment more or less during production, as shown in FIG. 10, a low-resistance portion arises as in the case of conventional pattern configuration.
FIG. 10a is a schematic cross-sectional view at a point in time when in the production flow of FIG. 7, the etching of the upper electrode 14 in Step S004 is completed and resist 21 is formed to etch the lower electrode 13. In the figure, there is a mismatch in mask alignment and the resist 21 applied when forming the lower electrode 13 is formed on the left side of the upper electrode 14 so as to overhang the lower electrode 13.
FIG. 10b is a schematic cross-sectional view at a point in time when in the production flow of FIG. 7, the etching of the lower electrode 13 is completed. As the result of the mask misalignment noted above, the resist 21 has failed to mask the upper electrode 14 in the step of etching the lower electrode 13, thus resulting in the overetching of an edge (right-side edge in the figure) of the upper electrode 14. Consequently, the edge (right-side edge in the figure) of the upper electrode 14 has shifted inward from an edge (right-side edge in the figure) of the lower electrode 13. Therefore, there has arisen a portion that cannot be etched due to the presence of resist 21 formed on the lower electrode 13 and an edge (left-side edge in the figure) of the lower electrode 13 has shifted outward from an edge (left-side edge in the figure) of the upper electrode 14.
FIG. 10c is a schematic cross-sectional view at a point in time when in the production flow of FIG. 7, the resist 21 has been removed after the lower electrode 13 is etched. Eventually, as illustrated in the figure, there has arisen an exposed portion in the lower electrode 13, resulting in the formation of a low-resistance portion (silicided portion).
Consequently, under the premise that a mismatch in mask alignment more or less occurs, it is not possible to precisely monitor the sheet resistance of the lower electrode even with Measurement Pattern 2.
As described heretofore, since the abovementioned two measurement patterns are either difficult to create or are not capable of completely shutting off the short-circuiting current path of a low-resistance portion, it is not possible to precisely measure the resistance value of the lower electrode. Hence, on the premise that there always exists a low-resistance component due to the abovementioned low-resistance portion (silicided portion), there are proposed measurement patterns whereby it is possible to analytically remove the low-resistance component and determine the sheet resistance of a high-resistance portion and an analysis method using the measurement patterns.